In a semiconductor integrated circuit, a MOS transistor that is driven with a higher voltage is often required as well as a MOS transistor that is driven with a low voltage. In cases where an input and output voltage of an external circuit is approximately 3.5 V, a middle breakdown-voltage MOS transistor that is driven with a voltage of approximately 3.5 V is required. Thus, a MOS transistor that is driven with a voltage higher than such a voltage may be required.
In a power amplifier transistor that is mounted in a transmission module of a portable wireless device, input of high radio-frequency (RF) electricity generally causes a voltage output from a drain electrode to be swung in an amount more than approximately double of a bias point. Accordingly, the MOS transistor requires an increased drain breakdown-voltage. A power amplifier mounted in the portable device is generally used in a frequency band in the range from hundreds MHz to several GHz. Accordingly, excellent high-frequency properties are also required at the same time. Not only in the portable device, but also in the power amplifier of high output and high frequency wave, a high breakdown-voltage and excellent high-frequency properties are often required.
In the MOS transistor in which the high breakdown-voltage and the excellent frequency properties are required, reduced on-resistance and an improved gain in the high frequency wave are required. A depletion layer is expanded between an effective channel region in which a gate voltage controls an electric current and a drain region in which a drain electrode has a contact, thereby achieving the high breakdown-voltage. In order to achieve the high breakdown-voltage, employment of a structure of an extended drain (ED) MOS transistor is effective, in which a length of a portion in which a lightly doped drain (LDD) region overlaps a gate electrode is increased with the result that the gate voltage helps the depletion layer to expand.
Even if the depletion layer is expanded, it is required that an effective threshold value is provided to preclude the occurrence of a punch-through-phenomenon. In order to provide the effective threshold value so as to preclude the occurrence of the punch-through-phenomenon, the increase of a dopant concentration in the channel region is effective. However, the uniform increase of the dopant concentration in the channel region likely causes the increase of the on-resistance. In a structure in which lateral distribution of a channel dopant concentration is modulated so as to be lowered toward a drain, the effective threshold value is provided in a region of a high dopant concentration, and a carrier is capable of being accelerated by a built-in electric field due to gradient of the dopant concentration. The on-resistance of the MOS transistor is decreased, and the high radio frequency electricity is likely to be improved. In a laterally diffused (LD) MOS transistor structure in which a channel dopant is added to a source and in which the dopant is thermally diffused in a lateral direction toward a drain, a structure is capable of being provided, in which the channel dopant concentration is gradually reduced from the source to the drain. However, in order to diffuse the dopant for a long distance, annealing is required to be performed at a high temperature for a long time.
There have been attempts to integrate the LDMOS transistor with the MOS transistor of a peripheral circuit. However, such attempts are incompatible with an advanced CMOS process of the 90 nm generation or later. In addition, in cases where the channel dopant concentration is increased in a source region, resistance is likely to be increased in the source.
On the basis of an example as an n-type metal-oxide-semiconductor (NMOS) transistor, Japanese Unexamined Patent Application Publication No. 6-310717 proposes a technique including: forming a gate electrode; implanting an n-type dopant to form an n−-type diffusion layer (extension region) with utilizing the gate electrode as a mask; covering a drain side with a mask; ion-implanting an n-type dopant into a source side to form an n-type diffusion layer in a source side; and rotationally ion-implanting a p-type dopant for forming a channel region at an inclination angle, thereby forming a p-type diffusion layer in the source side in order to cover the n-type diffusion layer in the source side. The p-type diffusion layer in the source side suppresses the expansion of the depletion layer, and therefore the punch-through phenomenon is capable of being suppressed to improve breakdown-voltage between the drain and the source.
In a technique disclosed in Japanese Unexamined Patent Application Publication No. 10-116983, a resist mask is used to perform the ion-implantation of As of the n-type dopant to a region which is included in an n-type silicon substrate and in which LDD will be formed, and then B as the p-type dopant is widely ion-implanted. Each dopant is simultaneously diffused by, for example, thermal diffusion at a temperature of 1200° C. for eight hours, thereby forming a p-type diffusion layer having a low concentration in a p-type well region, the p-type diffusion layer having a reduced effective concentration resulting from compensation of the n-type dopant. Subsequently, the n-type dopant, for example P, is ion-implanted into the p-type diffusion layer having the low concentration and then is thermally diffused at a temperature of 1200° C. for two hours, thereby forming an n−-type drain diffusion layer.